1. Field of the Invention
The present invention relates to an integrated semiconductor device on which multiple semiconductor chips are mounted.
2. Description of the Related Art
In the recent integrated semiconductor device technology, high-density integration technologies have been progressed, and semiconductor elements that constitute the integrated semiconductor device is required high integration accordingly. Especially in the recent technology for the integrated semiconductor devices, a high integration technology for micro electro mechanical systems (MEMS) is required along with for large-scale integrated (LSI) circuits.
The MEMS include electro mechanical components having a microstructure that is fabricated by silicon micro-fabrication process. The MEMS are expected to apply widely in the field of electronic components such as a pressure sensor, an acceleration sensor, and an RF filter. To integrate the MEMS with LSIs, a high-density three-dimensional packaging technology has been developed as one of MEMS-LSI integration technology, with which the LSIs and MEMS are laminated on one another. In this packaging, however, a vertical through hole has to be formed in the LSIs and the MEMS, which raises the device fabrication cost. Thus, a technology to integrate them on the same plane, which does not need to form the vertical through hole, is required.
The integration technology on a single plane includes two major methods; System on Chip (SOC) and System in Package (SIP). The SOC is a method of packaging by forming multiple elements on a single chip. The SOC method can increase the density of the element, but there is a limit to the elements that are integrated. For example, a Si device cannot integrate an element of a different type of devices such as GaAs because the device fabrication process is incompatible. Furthermore, the SOC takes long time for designing and realizing a new element, which increases device development costs.
On the other hand, with the SIP method, multiple LSI chips and MEMS chips are individually prepared, and then integrated on an interposer circuit board. In the SIP, there is no limit to the elements incorporated because the elements are individually prepared. Furthermore, in the case that a new system is developed, a conventional chip can be used so that the period of time required for designing can be reduced and device development costs can be reduced accordingly. However, the packaging density depends on the interposer circuit board on which the LSI chips and MEMS chips are mounted, and thus it is difficult to increase the device packaging density.
To solve the above problem, JP-A 2007-260866 (KOKAI), for example, suggests that LSIs and MEMS prepared by individual producing techniques are diced into chips after inspection and screening and then the chips are realigned side by side and redistributed into a MEMS integrated wafer. The redistributed MEMS wafer brings manufacturing costs down by allowing for the integration of elements of various types prepared by different producing processes and realigning on a large area only the operation elements that have passed the inspection. In addition, the LSIs and MEMS on the redistributed MEMS wafer are electrically connected to one another by a fine wiring layer. The pseudo-SOC technology, with which the LSIs and MEMS are realigned at a chip level and redistributed as an MEMS integrated wafer, can offer a high packaging density that the conventional SIP could never achieve and integration of different-type elements that the conventional SOC could never achieve.
With the pseudo-SOC technology, however, when a pseudo-SOC chip is mounted on the circuit wiring board by flip-chip technique, the pseudo-SOC chip may become deformed due to a difference between the coefficient of thermal expansion of the circuit wiring board and the pseudo-SOC chip. Then, an organic resin that insulates and supports the elements of different types may be broken. More specifically, a displacement difference appears due to the difference between the coefficient of thermal expansion of the pseudo-SOC chip flip-chip mounted by use of bump electrodes arranged on the periphery of the pseudo-SOC chip and the circuit wiring board that mounts the pseudo-SOC chip. This displacement difference causes a warp in the pseudo-SOC chip, and the organic resin that is provided between the different-type devices of the pseudo-SOC chip eventually is broken by stress. The main cause of the breakage is that I/O electrodes are arranged on the periphery of the pseudo-SOC chip to reduce the parasitic capacity by not arranging bump electrodes on the semiconductor element and to alleviate the bump electrode pitch.